The recent trend in designing a system LSI is that a system LSI is designed first at a high abstraction level and then an RTL description is generated through behavioral synthesis.
In this design method, the behavioral description, which implements the desired behavior of a system LSI, is designed first.
Next, the behavior simulation is performed to confirm if the designed behavioral description achieves the desired circuit behavior, that is, if the design is correct.
If the design is correct, the behavior description is transformed into an RTL description through behavioral synthesis.
When an LSI is designed using the design method described above, there is a requirement that the test vector used in the behavioral simulation is used also in the RTL simulation after the behavioral synthesis. For example, this requirement has first and second purposes described below.
The first purpose is to confirm if the behavioral description before behavioral synthesis and the RTL description after behavioral synthesis implement the same function.
If the behavioral description and the RTL description do not implement the same function, the behavioral simulation, if performed to confirm that the behavioral description achieves the desired behavior of the circuit, is meaningless. This is because the designed circuit does not eventually implement the desired behavior.
Conventionally, whether or not the behavioral description and the RTL description implement the same function is confirmed by using the same test vector for the behavioral simulation and the RTL simulation and comparing the results of both simulations.
The second purpose is to confirm the performance of the circuit after the behavioral synthesis.
Because time information is not usually included in the behavioral description, the circuit performance, for example, how much time is required to achieve a function, cannot be confirmed.
In contrast, the RTL simulation reveals how much time is required to achieve a function, that is, the RTL simulation shows the circuit performance.
Therefore, the related art technique checks whether or not the designed behavioral description achieves the desired performance by using the same test vector in both the behavioral simulation and the RTL simulation and evaluating the circuit performance measured in the RTL simulation.
The problem here is that the test vector used in the behavioral simulation cannot be used directly in the RTL simulation.
The reason is that the input application timing and the output observation timing differ between the behavioral simulation and the RTL simulation.
In general, there is no concept of timing (clock) in the behavioral description. Even if there is the concept of timing, the granularity of timing in the behavioral description is different from that of the RTL description. Therefore, the sequence of data that is used as the test vector in the behavioral simulation, if applied at each clock cycle during the RTL simulation, does not produce the same result as that produced by the behavioral simulation. Similarly, the output of the RTL simulation, if observed at each clock cycle, is not the same as that produced by the behavioral simulation.
Patent Document 1 (Japanese Patent Kokai Publication No. JP-P2005-78402A) discloses a behavioral synthesis system that solves the problems described above. The behavioral synthesis system described in Patent Document 1 is proposed primarily to solve the first problem described above (the sequence of data that is used as the test vector in the behavioral simulation, if applied at each clock cycle during the RTL simulation, does not produce the same result as that produced by the behavioral simulation). This conventional behavioral synthesis system assumes that the file read function, which reads the sequence of input from a file, and the file write function, which writes the sequence of output to a file, are described in the behavioral description. The file read function and the file write function are generically called a file function. This conventional behavioral synthesis system comprises syntax analysis means, control data flow graph construction means, scheduling/binding means, test bench generation means, and RTL generation means. The behavioral synthesis system having this configuration operates as follows.
That is, the syntax analysis means and the control data flow graph construction means leave the file functions, which are included in the behavioral description, undeleted.
Resource binding and scheduling are performed to create an RTL description based on the constructed control data flow graph.
The file input for a file function is represented in the created RTL description using the select signal of the multiplexer for input data. The file output condition is represented using the select signal of the multiplexer for output data.
However, the behavioral synthesis system described in Patent Document 1, which operates on the premise that the file functions are used in the behavioral description, is applicable only to a behavioral description satisfying this premise.
An example of the equivalence verification method is disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP-P2004-145712A). The equivalence verification method disclosed in Patent Document 2 is proposed primarily to solve the first problem described above. This equivalence verification method finds a comparison time based on the number of delay cycles from the time the input signal is determined to the time the output signal is determined in the RTL simulation result and compares the value of the output signal of the RTL simulation result with the value of the output signal of the behavioral simulation at the comparison time. The problem with this method is that the kind of circuit to which this method is can be applied is limited.
This is because no consideration is made in this method for a circuit whose input value application time differs according to the input signal.
In addition, no consideration is made in this method for a case in which the comparison time cannot be determined based on “the number of delay cycles”, for example, when the number of delay cycles depend on the input data.
Patent Document 3 (U.S. Pat. No. 6,845,341 B2) discloses a performance analysis system. The general operation of this performance analysis system is as follows. That is, a test bench for executing the behavioral simulation and the RTL simulation at the same time is created. A module for absorbing the difference in the input time and the output time of the behavioral simulation and the RTL simulation is inserted between the behavioral description and the test bench and between the RTL description and the test bench. In this configuration, the behavioral simulation and the RTL simulation receive the same test vector and the number of clocks required for the RTL description to execute simulation is measured to evaluate the performance.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-78402A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-145712A
[Patent Document 3]
U.S. Pat. No. 6,845,341 B2 (FIG. 2)
The above mentioned patent documents are incorporated by reference. The analysis on the related arts given by the present invention will be described in the below.
In the related art system, there is a problem that the test vector used in the behavioral simulation cannot be used directly in the RTL simulation.
This is because of the input application timing and the output observation timing as described above. The above discussion shows that various propositions for solving this problem are not satisfactory.
Another reason for the above problem is the sharing of input terminals and output terminals. In general, there is not always a one-to-one correspondence between the input/output terminals of a behavioral description and the input/output terminals of an RTL description.
A still another reason for the above problem is a behavior that cannot be represented by a behavioral description. There are many behavioral descriptions where the input/output behavior during a reset is not specified. For example, when the C language is used for behavioral description, the behavior of the input/output during a reset is not specified (there is also behavioral description language, such as SystemC language, in which the input/output behavior during a reset is specified).
This means that the application of an input value, or the observation of an output value, if performed during the reset period at RTL simulation, does not give the same result as that produced by the behavioral simulation.
A still another reason for the above problem is an external model (shared memory model, memory model, operation unit model, etc.). In behavioral synthesis, an array in the behavioral description is implemented by a memory in the RTL description, and a variable in the behavioral description is implemented by a register outside the module in the RTL description.
When an operation in the behavioral description is implemented by an operation unit in the RTL description, the operation is sometimes output as a black box whose detailed internal logic is omitted.
This means that, to perform the RTL simulation, a memory simulation model, a register outside the module, and an operation unit simulation model that is output as a block box must be prepared.
Accordingly, it is an object of the present invention to provide a behavioral synthesis apparatus, a behavioral synthesis method, and a behavioral synthesis program that allow a test vector, which is used before the behavioral synthesis, to be used also for a circuit obtained after the behavioral synthesis.
According to a first aspect of the present invention, there is provided a system (apparatus) comprising: input application/output observation timing signal generation means that creates an input application timing signal and an output observation timing signal for each input and output of a circuit and creates respective logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that applies an input to, and observes an output from, the circuit according to values of the input application timing signal and the output observation timing signal.
According to a second aspect of the present invention, there is provided a system (apparatus) comprising: test bench generation means that recognizes an input application timing signal and an output observation timing signal in a behavioral description of a circuit and generates a test bench that applies an input to, and observes an output from, the circuit according to values of the input application timing signal and the output observation timing signal.
According to a third aspect of the present invention, there is provided a system (apparatus) comprising: test bench generation means that generates a test bench that counts a number of clocks after a reset is released and, when the number of clocks matches a predetermined value, applies an input or observes an output.
According to a fourth aspect of the present invention, there is provided a system (apparatus) comprising: the test bench generation means that generates the test bench that does not apply an input or observe an output when a reset signal or a stall signal is effective.
According to a fourth aspect of the present invention, there is provided a system (apparatus) comprising: the test bench generation means that outputs the test bench that has a simulation model for a hardware resource that is output as a black box in an RTL (Register Transfer Level) description.
Also provided are the invention of methods and the invention of programs for the first to fifth aspects of systems (devices) described above.
The meritorious effects of the present invention are summarized as follows.
The present invention allows the same test vector to be used in a behavioral simulation and an RTL simulation. This is because, in the present invention, a test bench is output in such a way that a test vector used before behavioral synthesis can be used also in a circuit generated after behavioral synthesis.
Still other features and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein examples of the invention are shown and described, simply by way of illustration of the mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different examples, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.